Bias generator self-calibration video

2020-09-26 10:15 by Tobi

See how on-chip bias current generators can self-calibrate to improve matching by at least 3X

See the short summary video on YouTube or embedded below and the poster.

Congratulations to NSC masters student Zheming Yu for acceptance of this work with Tobi Delbruck. It finally completes the development of the on-chip bias generator calibration circuits included on the SEEBETTER DAVIS chips from ca. 2015.

Many neuromorphic chips now include on-chip, digitally programmable bias generator circuits. So far, precision of these generated biases has been designed by transistor sizing and circuit design to ensure tolerable statistical variance due to threshold mismatch. This paper reports the use of an integrated measurement circuit based on spiking neuron and a scheme for calibrating each chip set of biases against the smallest of all the biases from that chip. That way, the averaging across individual biases improves overall matching both within a chip and across chips. With the method presented in this paper, 1-sigma mismatch of subthreshold currents is decreased by at least a factor of 3. The firmware implementation completes calibration in about a minute and uses only about 1kB of flash storage of calibration data.

Bias calibration could increase yield of mass production devices by reducing the number of devices that fail testing with nominal programmed bias currents.